Verification Engineer

Verification Engineer (2 - 5 Yrs)

RESPONSIBILITIES:

Develop and tune the verification environment and methodology.Create test plans for both unit-level and chip-level environmentsDesign and implement design verification environmentsCode testbenches using Verilog and C PLIWrite tools in Perl and shell scripts Utilize advanced verification tools, formal verification, emulation, and code coverageGenerate tests and debug the Verilog design

MINIMUM REQUIREMENTS:

Minimum of 2 years experience in complex ASIC verification and/or ASIC design.Must be strong in C / C++, Verilog and Perl programmingKnowledge of SystemVerilog a plusGood communications skills and ability and desire to work as a team player are a must. Must possess good communication skills and the ability to work well as a team.Previous experience mentoring junior engineers a plus BE/ BTech, ME/MTech or PhD and CGPA of 8.0 out of 10.0 or equivalent scores are preferred

Plz send your updated resume with following details :
Current CTC :
Expected CTC :
Notice Period :
Current Location:
Willing to relocate to Bangalore, Pune, Hydrabad & Noida :
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