Senior Engineers with following profile:-
Bachelors/Masters in ECE/EE
- 2 - 5 years experience in frontend ASIC design and debugging
- Must have worked with on multi-million gates SoC
- Well conversant with SystemVerilog, Verilog, VHDL, C, System-C - Hands-on with industry standard frontend EDA tools QuestaSim, Synthesis etc.
- Excellent Communication skills, Customer management and inter
-personal skills
Preferred:
- Emulation experience
- Signed off 3-4 multi-million gate complex SoCs
- Conversant with Mentor Graphics AVM/OVM
- Conversant with industry standard protocols viz. PCI Express, USB, SATA etc
Plz send your updated resume with following details :
Current CTC : Expected CTC : Notice Period : Current Location:
Willing to relocate to Bangalore, Pune, Hydrabad & Noida :
Reason for change:
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