Senior Engineer - VIP

Senior Engineer - VIP

The candidate should:
Be an integral part of a team that is developing checkers and protocol monitors, such as PCI Express and 10 Gigabit Ethernet, for use with 0-In's advanced functional verification tools and Questa RTL simulation. 0-In's checkers and monitors help design teams find more bugs in less time than conventional simulation techniques.

Requirements:
Solid Verilog HDL RTL knowledgeSolid RTL simulation and test bench experienceIntimate knowledge of one or more standard bus protocolsSolid engineeringMS/BE and 3+ years in electrical engineering or related field

Desired:
Experience with cycle-based simulation and constrained-random simulationKnowledge of assertion languages or libraries, such as PSL, SVA, OVLVHDL & System Verilog HDL RTL knowledgeExperience with System C or C++Experience with Specman Elite or Vera/NTBExperience with Formal Property Verification tools

Plz send your updated resume with following details :
Current CTC :
Expected CTC :
Notice Period :
Current Location:
Willing to relocate to Bangalore, Pune, Hydrabad & Noida :
Reason for change:

Reply Soon,
newsoftindia@vsnl.net

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