Front-end Design
Experience: 2-5 yearsQualification: Bachelor s engg degree in EE, ECE or Instrumentation-
Well-versed with synthesizable behavioral logic implementation using Verilog.
- Experience with simulation and debug using ModelSim/VCS and Debussy.
- Sound knowledge and experience with Synopsys Design Compiler based synthesis of relatively large high
-performance designs.
- Experience and strong knowledge on all aspects of Static Timing Analysis using Primetime.
Additional Preferred Qualifications:
- Experience with chip-level RTL integration of relatively large SOCs.
- Experience with using Equivalence checker tools like LEC.
- Knowledge on Design For Test and Manufacturability (DFTM) aspects.
- Knowledge on design implementation using VHDL will be an advantage.
- Experience with verification and test-bench development.
Complex Tasks:
Large IP designs in typically have very tight performance and power/area targets set by the high-volume high-performance markets, and high configurability for catering to the needs of a wide-variety of target applications. Meeting such conflicting requirements often demands extensive planning and pure innovation.
Most SOCs that are being developed integrates any where in the order of 100 IP modules that are implemented across world-wide. The SOC integration role offered by this position involves managing communication with the world-wide IP providers in defining the chip requirements accurately for such large number of IPs and also ensuring on-time delivery/integration into the SOC.
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Willing to relocate to Bangalore, Pune, Hydrabad & Noida :
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